Netgen 1.4

Revision information on Netgen:

Netgen revision history: Version 1.1
  1. December 14, 2002
    This is a first draft. Only a few things have been changed in this release other than the Tcl/Tk port. There is now support for capacitors, resistors, bipolars, poly-poly capacitors and resistors built with the pseudo-poly layer in magic, in the SPICE, sim, and ext format read routines. The Tcl version has a completely revamped command set, better matching the general practices of Tcl command syntax (mainly meaning commands are full words rather than single letters). In addition, the command sets for "netgen" and "netcmp" have been combined.
  2. January 13, 2003
    Massive speedup of several critical and badly-written functions; reduced from O(N^2) to O(N). The "compare" command is now virtually instantaneous. Commands "nodes" and "elements" now give more relevant information regarding specific points in the network. "sim" format retains position in the element names (for FET and FET-like elements) for convenient traceback to a layout or schematic.
Netgen revision history: Version 1.2
  1. March 12, 2003
    Fixes the the "make config" process for Tcl/Tk compile. Also, finished implementing the Tcl "log" command for log file output, and added the script-level "lvs" command to replace the original standalone program "netcomp".
  2. March 24, 2003
    Corrections to TCL command interface.
  3. March 26, 2003
    This version was never officially released.
  4. March 31, 2003
    Changes for interoperability with magic and IRSIM.
  5. April 3, 2003
    Changes to save position information in element names for transistors read from .sim files.
  6. September 22, 2003
    Added the capability to handle "M=" syntax in SPICE files for declaring multiple transistors with equal size and connections.
  7. September 30, 2003
    Fixed an unfortunate problem with the "lvs" script command in which it implies that circuits which pass the low-level connectivity comparison match correctly. In fact, these circuits may have errors. The fix checks this condition, performs the high-level resolution of automorphisms, and reports a final pass/fail condition.
Netgen revision history: Version 1.3
  1. November 15, 2004
    Changed the "make" method to GNU autoconf. Revised the directory structure to put most of the Tcl-based stuff into the "tcltk" subdirectory. The source itself is essentially unchanged from version 1.2. Confirmed compile and run for both the Tcl and non-Tcl versions.
  2. August 6, 2005
    Updated parts of the "make" process to match additions to magic and xcircuit, and to address issues related to compile and install on Cygwin. Cygwin users should read the compile and install instructions on magic for Windows.
  3. September 3, 2005
    Added Xilinx support. Thanks to Peter Welch for providing the patch files. Thanks to Ingo Cyliax for the code itself, which was added to a branch of netgen at the University of Indiana, and about which I was unaware until Peter brought it to my attention. Apparently that code branch is no longer available for download from the CS department at Indiana.

    Also: Changed the Makefile process to parse the file VERSION for version and revision information, not the directory name. Switched the directory to the name with the version number ("netgen-1.3.2") and the symbolic link to the package name ("netgen"). It was gently pointed out to me that I had this ass-backwards.
  4. September 6, 2005
    Added support for reading bipolar transistors from SPICE decks.
  5. September 7, 2005
    Made some changes to prevent crashing on unexpected input (in particular, undefined subcircuits) in SPICE decks. Also, added the command "readlib" for reading Actel and Xilinx libraries (formerly required use of "readnet actel|xilinx" plus an unused dummy argument, due to an error in the Tcl command-line processing). A warning is posted if an attempt is made to write a Xilinx or Actel format file without first reading the associated library.
  6. Februrary 23, 2006
    Distribution compliance changes: CAD_HOME redefined to be the same as "libdir", so that "libdir" can be defined independently of "prefix" when running configure without screwing up everything.
  7. Februrary 24, 2006
    Changed CAD_HOME to CAD_ROOT to avoid breaking backwards compatibility.
    Also: Added DESTDIR to all the Makefile install procedures to support "sandbox" compilation and installation.
  8. June 14, 2006 at 2:40am
    Initial revision
    Also: source distribution
    Also: Added distclean target and dist target Added RPM spec file
    Also: Removed extra configure logs
  9. November 22, 2007 at 2:40am
    Added handling for device types "z", "r", "c", and "b" when using the netgen command "writenet sim". However, device properties (length, width, resistance, etc.) are still not handled. . .
  10. November 23, 2007 at 2:40am
    Added rudimentary support for device properties. For the moment, apart from the important aspect of having a database representation for device properties such as length, width, resistance, and capacitance, there is support for reading device properties from SPICE files and writing those that are supported by the sim format to .sim files. It is my intention to eventually support property comparisons in LVS.
  11. December 1, 2007 at 2:40am
    Corrected some errors where strdup() and free() were called instead of their Tcl counterparts.
Netgen revision history: Version 1.4
  1. Nov 24, 2007 at 4:55pm
    Initial check-in of the development distribution. Added automatic test of SPICE file format for "readnet". Added true 4-port and 2-port devices. Added read-in of device properties. Eliminated built-in device classes; all device classes are generated on the fly as the file is read in. For SPICE decks, the device model becomes the device class, so that different device models are compared independently. Added command option "equate classes" to force equivalence between device classes in different circuits. Added "lvs" command option to read in a file of class equivalences.
  2. November 26, 2007 at 2:40am
    Made some corrections to avoid confusing properties with nodes of the same name, and to simplify the printout of "contents ". Some simple tests indicate that LVS is working correctly with subcircuit calls (spice X records).
    Also: Corrected an error that causes netgen to hang if "lvs" is given a bad filename.
  3. December 3, 2007 at 2:40am
    Many, many changes. Implemented a set of internally-defined device classes that encompasses pretty much everything (mostly based on SPICE device model types), with some differences such as a distinction between 3- and 4-terminal FETs, and similar items. This internal type also encompasses the original "primitive" flag, in that the internally-defined "subcircuit" device is distinguished as the only non-primitive device. Completely reworked device properties (again) such that only specific properties (e.g., length, width, capacitor and resistor value) are checked, and these are mapped into type double and kept separate from other properties for quick comparison during LVS. Reworked permutation to allow "standard" permutations of source/drain on any device recognized internally as a FET, and endpoints on internally-defined resistor classes, as well as allowing (via script command) permuations to be defined on any pins of any device class. Unfortunately, at the moment, the LVS itself is hosed, as a result of one or more of the above changes. The ability to translate between netlist formats is currently rather limited, the most complete being the reading of SPICE format files and the writing of "sim" format files. Diodes, inductors, and transmission line models are not yet handled in SPICE input.
  4. December 10, 2007 at 2:40am
    More changes. . . changed the "class equivalences" file passed to the "lvs" procedure to a Tcl script setup file, in which class equivalences would be merely one possibility. Permutations as yet cannot be handled here because the permutations currently act upon the netcmp database, and so must be run after the "compare" command; whereas the setup file is executed prior to "compare". Changed the way device properties are handled, so that properties "of interest" to LVS are listed in the cell definition, duplicated in a separate list in each instance, and converted to type double (floating-point) where appropriate. The "properties of interest" are defined at the time the cell definition is created. There needs to be a method to add or subtract the "properties of interest" from the cell definition. Changed the way device models are handled, replacing the "primitive" flag with a value indicating an internal model type. Corrected read/write routines for sim and SPICE files, including correct handling of device models and properties, and unmodeled vs. modeled resistors and capacitors.
    Also: Changed the "permute" command such that it generates a list of pins to permute, but the actual permuation is punted until the element and node classes have been created. This allows the "permute" command to be issued in the setup script.
    Also: Corrected property error checking, which now appears to be correct, at least as verified by running on a few simple examples. Added the capability to specify the degree to which values are required to match (the "slop"), although for now this is set to the default value of 1%, and there is no way to change it (eventually a command will be added to manage property comparison).
    Also: Updated the TO_DO list.
    Also: A couple more corrections to property checks, to make sure that cells are considered matching if their classes are marked as corresponding.
    Also: Added a few corrections for handling nested spice subcircuit definitions. This allows LVS to run correctly on hierarchically-defined files, although for now only the topmost circuit is checked.
  5. December 29, 2007 at 2:40am
    Corrections that I failed to check into CVS last time. In particular, the malloc/free routines are all now correctly assigned to Tcl equivalents.
  6. December 30, 2007 at 2:40am
    Correction in property-checking code to prevent crashes when no properties are specified (namely, on the last device in the list).
  7. December 31, 2007 at 2:40am
    Basic hierarchical LVS has been implemented. However, a lot of cleanup is needed with regard to the output it produces!
  8. March 10, 2008 at 2:40am
    Corrected an error that causes netgen to announce property errors when there are no properties (this will happen on the last device in the netlist, and shows up when the order of the last device is different in the two netlists).
  9. May 23, 2008 at 2:40am
    2008-05-22 17:20 tim Corrected the "package require -exact Tk" problem in tkcon.tcl, which has already been corrected in the magic and IRSIM distributions. The fix is necessary to run the Tcl/Tk-based version with Tcl/Tk version 8.5.
  10. July 7, 2008 at 2:40am
    2008-07-06 11:24 tim Added /usr/share/tcltk to the search path for Tcl and Tk in the configure script, to conform to recent distributions of Ubuntu Linux.
  11. May 21, 2009 at 2:40am
    2009-05-20 08:56 tim Corrected an error found by Kan Chu in which a spice instance name followed immediately by a continuation line is not parsed correctly (the continuation line "+" is passed on as the first pin connection).
  12. May 25, 2009 at 2:40am
    2009-05-24 17:46 tim Corrected the SPICE read functions to (1) correctly handle the "+" continuation line character, and (2) handle carriage-return-linefeed characters from DOS-style text files.
  13. July 28, 2009 at 2:40am
    2009-07-27 06:47 tim Corrected SPICE read-in of semiconductor resistors and capacitors, which should not have a value in front of the model name.
    Also: Additional correction, due to the fact that the syntax of the semiconductor resistor and capacitor models in the standard SPICE documentation conflicts with the example provided underneath. Is the device value mandatory, optional, or prohibited?
  14. August 28, 2010 at 2:40am
    2010-08-27 18:01 tim Numerous changes supporting hierarchical LVS and the ability to read in files with subcells of the same name and keep them distinct. Also, added the ability to compare subcells of files from the "LVS" command, which avoids problems when one or both files come from "library" type GDS files without a top-level cell.
  15. December 21, 2010 at 2:40am
    2010-12-20 17:15 tim Major changes to support hierarchical LVS. Finally encoded routines to sort out port ordering between the schematic and layout circuits. Many issues still to be resolved, but netgen has now successfully run LVS on a magic-extracted hierarchical SPICE deck vs. an xcircuit-generated (schematic capture) hierarchical SPICE deck. Much hand-editing was required. Should resolve these issues over the next several weeks.
  16. December 24, 2010 at 2:40am
    Updated compare routines to ignore disconnected nodes in either circuit's netlist. Also: Modified the SPICE read routine to rename instance pin references after read-in when the instance was called before the cell was defined.
  17. May 26, 2011 at 2:40am
    Corrected an error that generated record 'x' into the output for all device types unknown to the .sim format (fallout from experimental handling of subcircuits in .sim).
    Also: Correction to prevent segfaults on encountering unknown device models.
  18. May 29, 2011 at 2:40am
    Corrected a non-initialized variable which causes known model types such as "diode" in a spice file to be overwritten with a subcircuit class, causing confusion with the hierarchical LVS.
    Also: Update at Sat May 28 06:19:36 PDT 2011 by tim
    Also: Merge branch 'master' into work
  19. May 30, 2011 at 2:40am
    Updated netgen-1.4 to my most recent development fixes/additions, a number of which had not been committed.
    Also: Update at Sun May 29 12:10:13 PDT 2011 by tim
    Also: Merge branch 'master' into work
  20. June 10, 2011 at 2:40am
    Script files regenerated from sources. Changes in this commit are probably not meaningful.
    Also: Update at Thu Jun 9 07:05:10 PDT 2011 by tim
    Also: Modified .gitignore to avoid creating a new revision for changes to logfiles and regenerated script files.
    Also: Merge branch 'master' into work
  21. October 27, 2011 at 3:00am
    Correction to netgen-1.4 to deal with undefined "CONST84" in Tcl code.
    Also: Update at Wed Oct 26 05:20:40 PDT 2011 by tim
    Also: Merge branch 'master' into work
  22. October 30, 2011 at 3:00am
    Corrected a bad error in sim files where transistor gate and drain are swapped on read-in.
    Also: Update at Sat Oct 29 11:39:14 PDT 2011 by tim
    Also: Merge branch 'master' into work
    Also: Redid the previous correction, changing the arguments in the subroutine instead of in the call, since it's the subroutine argument order that got changed, somehow.

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Last updated: October 30, 2011 at 3:00am