Netgen 1.4

Version 1.4.0 is a first cut at transferring the principle netlist for LVS from sim to spice format, removing the built-in device classes in favor of building device classes on the fly from device models as the file is being read. Version 1.4.0 supports 4-terminal devices, and true 2-terminal capacitors and resistors. It reads and writes device properties, although the LVS does not yet support comparison of device properties. It properly parses continuation lines in SPICE files. It auto-detects SPICE files from the first character "*" in the first line, not from file extensions. Later revisions will expand on LVS with subcircuits and hierarchy, and comparison of properties.

Version 1.4.5 completes the initial implementation of property matching, although some additions are needed to allow a detailed setup of non-default properties to match.

Version 1.4.6 implements true fully-hierarchical LVS. Revision 6 is a first cut at the LVS hierarchy, and some substantial work is required on presentation of the results. However, the basic method is in place. Cells that either match by name or are declared matching in the setup file are matched separately, while subcircuit cells whose matching cell in the opposing top-level circuit is unknown are flattened. Additional work is needed to check the port order of the two calls, and force a correct mapping between them.

Version 1.4.14 adds the port ordering feature. Netlists derived from two sources that may not agree on the order of ports to a cell can be matched by re-ordering the ports in one netlist to match those of the other, after the cell contents have been compared and verified.