[Xcircuit-dev] Multiple-gate chips in PCB netlists

[Stephen Hughes]

Hello,

  I would like to thank all responsible for "XCircuit" and "PCB".

  I have taken on the challenge of creating an xcircuit library containing 
the entire "unique" 7400 series of ICs.  Please inform me if this task has 
already been started by another.

  While working on the library I have come across a few peculiarities I 
thought would be of some interest.  These are in reference to multiple gate 
chips available in xcircuit-2.5.2 and above.

1)  Consider the case of the 74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input 
AND-OR-INVERT Gates.  If you do not have your data book handy :

U1-1: Two, 2-Input AND with outputs connected to a 2-Input NOR
U1-2: Two, 3-Input AND with outputs connected to a  2-Input NOR

I am curious as to a possible soloution to this problem.  Clearly a "libinst" 
placed in the library file would only duplicate one of the gates.  If each 
half of this device were created as an individual library part we would have 
the situation which I will describe next.

2)  I placed multiple instances of the 7473 component from my 7400 library 
onto a page with no connections between the gates and selected "Netlist -> 
Write Pcb".  The output was similar to that described in the tutorial:

ext1        U2-2-7
ext2        U2-2-8
ext3        U2-2-9
ext4        U2-2-10
ext5        U2-2-6
ext6        U2-2-5
ext7        U1-1-14
ext8        U1-1-13
ext9        U1-1-12
ext10       U1-1-3
ext11       U1-1-2
ext12       U1-1-1

The Info pin on the device is "pcb:U parameter(1)<?>-parameter(2)<1>".  As 
expected the parameters were updated with an assigned value for "?" and with 
and index value beginning with "1".  

Unfortunately, the netlist clearly shows two unique devices, much the same as 
if I had created two parts in the library with Info pins "pcb:U 
parameter(1)<?>-1" and "pcb:U parameter(1)<?>-2".  This ties in with the case 
of multiple but differing gates in a single IC package as in #1 above. I  am 
assuming the ICs in this example should be labled as U1-1-"pin" and 
U1-2-"pin".  Is the above netlist format a condition of the "PCB" program?

  One possible soloution would be to include the "libinst" inside the "{}" of 
the library object and if there is the concept of variables and scope the  
variable "?" would be the same within each object definition.  This would 
solve #2.

  The other possible soloution would to allow multiple gate definitions 
within the object definition.  This could perhaps use the 
"begingate...endgate" tags for the main object and then add 
"beginvirtualgate..endvirtualgate" for each instance where the gates are 
dissimilar in each IC package.

  I hope this message was informative and thought provoking.  I will submit 
the 7400 series library file in the near future.

Sincerely,

Stephen Hughes,
Honeycomb Electronics, Audio and Research, Inc.

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