[Xcircuit-dev] Problems of generating ".sim" file

[katherine]

Dear developer,

According to the Xcircuit -Schematic capture tutorail, I try to draw the Transconductance amplifier as illustrated.

However when I try to generate the ".sim" file for LVS, the output file shows as follows:

    sim circuit "wramp" from XCircuit v1.00
240
240
240
240
-288
-288
16
16
-160

I have no idea about that! The SPICE file looks good. Thus, I am wondering if the sim file of MOS in analoglib3 are incorrect, could you point out how can I generate the correct ".sim" file?

Besides, I think the generated ".sim" file seems exclude the size(W/L). Could you explain how does the Netgen-LVS goes without comparing the size?? 


Best Regards,

Katherine Shih
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