[Xcircuit-dev] RE: XCircuit ideas

[R. Timothy Edwards]

Dear Svenn,

   Thanks for your well-reasoned comments on xcircuit.  Here are some
responses.  Note that I just had a meeting with Steve Frezza at Gannon
University, and we're starting to integrate his automatic schematic
generation (ASG) code into xcircuit, along with a parser for reading
hspice.  This will take up most of my time for the next month, so
other development will have to wait.  However, your ideas are good
ones and I will give them due consideration when I have time to think
about things other than ASG.

> I haven't come this far yet so it is interesting to know, but xcircuit
> do export to pcb, and I have seen a EDA suite (BAE by Oliver Bartels)
> that can set properties (as a special symbol, a flag) on a wire and
> then the user can give properties to a signal wire that will be
> communicated to the pcb part. I'll have to play with the label function.

I thought more about this on my boring 4-hour drive to Pittsburgh, and
decided that the label and parameter functions of xcircuit are not likely
to do much for you.  I am much more a VLSI designer than a PCB designer,
myself.  About the only thing I know about schematic capture for PCB
designs is the PCB netlist, and unless there are extensions I don't know
about (entirely possible), there's no way to specify more than the
connectivity of the circuit wiring in the netlist file.  What you're
talking about would probably require using EDIF as the netlist format.
I have looked at some EDIF for VLSI work, but not for PCB.  So far, I
haven't done anything about writing a netlist output interface for
either.  I would need to look at some examples of EDIF written for PCB
netlists to get an idea how to write the interface for xcircuit.  EDIF
is a huge and complicated format which covers just about everything in
the universe, so it's necessary to look at only the subset of the EDIF
format needed for writing PCB or VLSI netlists.

> Is it then possible to assign bundled signal names to a graphical wire
> and place a porthole on a symbol and then inside the symbol expand
> those bundles? For top-down design, I really see a need for the
> possibility to hide the well of signal names that may turn up in the
> design of integrated circuits. Otherwise the symbols get to large.
> This is just a thought.

Not really.  There are ways to "fake" it, but I recognize that this
feature is one of the several important features lacking in xcircuit.
Again, this comes from my VLSI background;  analog designs rarely use
buses.  Probably the easiest way to do this is the "standard" way of
using the format "(a:b)" or "[a:b]" on a pin.  But xcircuit will need
the cabability to parse that format and produce the correct netlist
representation.

> Would it make sense that when I enter a part of a multi sheet toplevel
> that part can again be a multi sheet sublevel so that when I press
> shift-P at this level I get an overview of the schematics of this
> level only?

Since I just wrote the multi-page extension a couple of weeks ago, I
haven't thought about presentation.  But it probably makes sense to have
a "filter" on the page directry (shift-P) that can allow you to see only
the pages belonging to the current schematic.  At least, that's something
trivial that I can add easily.  A more comprehensive presentation of the
circuit hierarchy would take more time to work out.

> By the way, is xcircuit intended for larger designs (thousands of
> transistors) or will it be a documentation and small project tool? 

I have used xcircuit myself to do LVS on designs with tens of thousands of
transistors.  But generally speaking, most engineers prefer to move to
VHDL or Verilog to describe large designs.  The ASG functionality that
Steve and I are adding to xcircuit will be useful for taking a design in
a format like Verilog, and reading the netlist into xcircuit to view the
routed design in detail.

						Regards,
						Tim


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