globals {
   {{Font Times-Roman} {Text GND}} -2 
   {{Font Times-Roman} {Text Vdd}} -1
}

circuit {
   {
      name pmos
      ports {1 2 3}
      devices {
         {
	    {{Font Times-Roman} {Text {spice:M%i %pD %pG %pS Vdd pmos}}}
            {{Font Times-Roman} {Text {sim:p %pG %pS %pD}}}
         }
      }
      nets {
         1 {{Font Times-Roman} {Text S}}
         2 {{Font Times-Roman} {Text D}}
         3 {{Font Times-Roman} {Text G}}
      }
   }

   {
      name nmos
      ports {1 2 3}
      devices {
	 {
	    {{Font Times-Roman} {Text {spice:M%i %pD %pG %pS GND nmos}}}
	    {{Font Times-Roman} {Text {sim:n %pG %pS %pD}}}
	 }
      }
      nets {
	 1 {{Font Times-Roman} {Text G}}
	 2 {{Font Times-Roman} {Text S}}
	 3 {{Font Times-Roman} {Text D}}
      }
   }

   {
      name nor
      ports {1 4 3}
      calls {
	 {
	    name pmos
	    ports {-1 14 4}
	 }
	 {
	    name nmos
	    ports {4 -2 1}
	 } 
	 {
	    name nmos
	    ports {3 -2 1}
	 }
	 {	
	    name pmos
	    ports {14 1 3}
	 }
      }
      devices {{} {}}
      nets {
 	 1 {{Font Times-Roman} {Text Y}}
	 4 {{Font Times-Roman} {Text A}}
	 3 {{Font Times-Roman} {Text B}}
	 14 {{Text ext14}}
      }
   }

   {
      name SRflipflop
      ports {2 6 3 4}
      calls {
         {
	    name nor
	    ports {4 3 2}
	 }
	 {
	    name nor
	    ports {3 6 4}
	 }
      }
      devices {{} {}}
      nets {
	 2 {{Font Times-Roman} {Text S}}
	 6 {{Font Times-Roman} {Text R}}
	 3 {{Font Times-Roman} {Text Q}}
	 4 {{Font Times-Roman} Overline {Text Q}}
      }
   }

   {
      name sr_ff_use
      calls {
	 {
	    name SRflipflop
	    ports {1 2 3 7}
	 }
      }
      devices {{}}
      nets {
	 1 {{Font Times-Roman} {Text Set}}
	 2 {{Font Times-Roman} {Text Reset}}
	 3 {{Font Times-Roman} {Text Out}}
	 7 {{Text ext7}}
      }
   }
}