Challenge #2 (IHP SG13CMOS5L) is underway; the proposal field closed in August 2026 and schematic design is in progress, ahead of a November 9, 2026 tapeout. Challenge #3 (Wafer.Space GF180MCU) is currently accepting proposals, due August 31, 2026, ahead of a December 14, 2026 tapeout.
Challenge #3 detailed milestones: Wafer.Space GF180MCU
Challenge #3's Wafer.Space tapeout date is now set, so this schedule is fixed.
| Date | Milestone |
|---|---|
| Aug 17, 2026 | Challenge launches |
| Aug 17–31, 2026 | Write proposals |
| Aug 31, 2026 | Proposals due |
| Aug 31–Oct 5, 2026 | Schematic design & pre-layout verification |
| Week of Oct 5, 2026 | Schematic design review |
| Oct 5–Nov 2, 2026 | Layout & post-layout verification |
| Week of Nov 2, 2026 | Layout design review |
| Nov 2–Nov 23, 2026 | Chip top-level integration |
| Week of Nov 23, 2026 | Final design review |
| Dec 14, 2026 | Wafer.Space tapeout |
| Dec 21, 2026 | Test prep work begins |
| May 31, 2027 | Return from manufacture |
Post-tapeout milestones (packaging, shipping, and testing dates) will be added once set.