Challenge #3 (Wafer.Space GF180MCU) is currently accepting proposals, due August 31, 2026. See the Challenge #3 page and its Rules & Regulations before you write yours. Challenge #2 (IHP SG13CMOS5L)'s proposal field is now closed; see Challenge #2 for its status.
Steps to get involved
Follow the forum
Keep up with announcements and discussion at fossi-chat.org/#chipalooza. All changes to challenge terms are posted there first.
Let us know you're interested
Fill out the short interest survey below so we know who's planning to participate.
Send in your proposal
Email your written proposal to Open Circuit Design by the posted due date. See requirements below.
Submit your proposal
Proposals go to:
chipalooza@opencircuitdesign.com
Your proposal document should include:
- The type of IP block
- List of I/O, including test ports. Note any special requirements such as low resistance to the pad.
- Functional description of the IP block
- A target specification with all relevant characteristics (average, minimum, maximum values as appropriate, and absolute limits)
- An outline of a test plan for validating the IP block through measurement
Sent as separate attachments (not part of the main proposal document):
- List of any equipment available for use in testing
- CVs of the designers
Leave personal and institutional details out of the main proposal document. It will ultimately become part of the IP block's public documentation. Full details in each challenge's own Rules & Regulations page (see Challenge #3, currently accepting proposals).
Take the survey
Let us know you're interested in participating, even if your proposal isn't ready yet:
